SE97B_1
?NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 27 January 2010
23 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
8.2 CAP Capability register (00h, 16-bit read-only)
Table 10. CAP - Capability register (address 00h) bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
RFU
Default
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
EVSD
TMOUT
VHV
TRES
TRES
WRNG
HACC
BCAP
Default
1
1
1
1
0
1
1
1
Access
R
R
R
R
R
R
R
R
Table 11. Capability register (address 00h) bit description
Bit
Symbol
Description
15:8
RFU
Reserved for future use; must be zero.
7
EVSD
EVENT
with shutdown action.
0 The EVENT
output freezes in its current state when entering
shutdown. Upon exiting shutdown, the EVENT
output remains in the
previous state until the next thermal sample is taken.
1 (default) The EVENT
output is de-asserted (not driven) when
entering shutdown, and remains de-asserted upon exit from
shutdown until the next thermal sample is taken.
Remark: Bit 7 follows the state of SMBUS[4] which can change
EVENT
output to freeze.
6
TMOUT
Bus time-out period for thermal sensor access during normal
operation. Note that bus time-out support is operational in shutdown
mode, or for access to the EEPROM portion of the device.
1 Parameter t
to(SMBus)
is supported within the range of 25 ms to
35 ms (SMBus compatible).
5
VHV
High voltage standoff for pin A0.
1 Supports a voltage up to 10 V on the A0 pin.
4:3
TRES
Temperature resolution.
10 0.125 癈 LSB (11-bit)
2
WRNG
Wider range.
1 can read temperatures below 0 癈 and set sign bit accordingly
1
HACC
Higher accuracy (set during manufacture).
1 B grade accuracy
0
BCAP
Basic capability.
1 has Alarm and Critical Trips interrupt capability
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